Abstract: | Global Positioning Systems (GPS) and other emerging Global Navigation Satellite Systems (GNSS) are expected to provide accurate location information for various communication and navigation applications. GNSS works well under a wide variety of conditions, but reception is often challenged in narrow urban canyons with tall buildings blocking the signals, indoors or in tunnels and underground locations. Recently software defined GPS receivers (GPS-SDR) have become popular as they facilitate receiver adaptation to various signal conditions, provide a complete algorithmic control to developers and reduce development complexity for a broader technology community. The Universal Software Radio Peripheral (USRP) is a popular, affordable RF Front-End used by SDRs for capturing GPS signals. This and other similar front-ends evolve to provide more on-board accelerating capabilities through DSPs and FPGAs for computationally intensive tasks. By delegating demanding tasks SDRs will be able to process weaker signals and shorten position computation cycles. While increased computational resources provide acceleration opportunities, one should take into account that, for multimode GPS-SDR operations, the required resources may vary and reconfigurable, scalable accelerator solutions will be needed. This paper proposes reconfigurable FPGA implementations for acquisition and tracking block correlators. |
Published in: |
Proceedings of the 24th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2011) September 20 - 23, 2011 Oregon Convention Center, Portland, Oregon Portland, OR |
Pages: | 3720 - 3728 |
Cite this article: | Suleiman, Adnan, Kinjarapu, Dushyanth, Akopian, David, Hudson, Fred, "Reconfigurable Correlator Accelerators for Software GPS Receivers," Proceedings of the 24th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2011), Portland, OR, September 2011, pp. 3720-3728. |
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