Dynamic Phase Lock Loop for Robust Receiver Carrier Phase Tracking

Karl Shallberg, Tom Morrissey, Joe Grabowski, Michael Olynik

Abstract:	WAAS reference receivers in Alaska have had their carrier phase lock loop (PLL) lose lock and at times false lock on a side lobe of the desired signal, the latter resulting in an offset in output velocity / Doppler and a corresponding ramp error in output Accumulated Delta Range. It is believed that such behavior is due to significant dynamics being imparted to the received GPS and WAAS signals by rare ionospheric anomalies. Laboratory tests performed at Zeta with input signal perturbations approximating those induced by ionospheric phase scintillation have also exhibited this false locking behavior. Such occurrences could be mitigated by increasing the receiver PLL bandwidth since increasing tracking bandwidth is a well known method for achieving more robust phase tracking in the presence of phase scintillation and other forms of dynamic stress. However, utilization of a larger PLL bandwidth would be at the expense of robust tracking performance in the presence of amplitude scintillation, interference, and random noise and therefore would potentially decrease WAAS service availability. A simple technique for mitigating such lost lock / false lock phenomena in high scintillation environments without compromising tracking performance under high noise and interference conditions is under investigation and is being considered for implementation in WAAS. This technique, denoted as Dynamic Phase Lock Loop (DPLL), consists of using a default PLL bandwidth under nominal conditions then switching to a higher PLL bandwidth whenever the magnitude of the carrier loop discriminator error signal exceeds a given threshold. Such adaptive bandwidth techniques have been investigated previously by Legrand (2001), Lian (2005), and Skone (2005), though these latter techniques are relatively complex and consist of dynamically / iteratively solving for, and adapting to, optimum bandwidths based upon data-derived estimates of noise and dynamic loop stress. The D-PLL algorithm can be simply described in a few lines of logic characterized by the following parameters: a low bandwidth value, a high bandwidth value, an error signal threshold, a carrier-to-noise density ratio below which the high bandwidth state is not allowed, and a minimum time duration for the high bandwidth state that is required to prevent excessive toggling between the high and low bandwidths. This logic operates at the PLL’s (20 msec) update rate and is embedded in between the PLL carrier loop discriminator and the carrier loop filter, thus allowing designation of the high or low PLL bandwidth value at every such update. A high fidelity computer simulation of the D-PLL using a four quadrant arctangent discriminator and a third order carrier loop filter was developed to characterize loop performance as functions of the dynamic stress environment, the input noise level, and D-PLL algorithm parameter values. Simulation results were encouraging in that: (a) robustness to phase scintillation was significantly increased; (b) D-PLL adaptation using the error signal was rapid enough to mitigate sudden increases in dynamic stress; and (c) there were no significant transients (e.g., ringing) induced in the PLL due to the switching between the high and low bandwidth states. As an aside, the simulations were able to reproduce conditions for which the PLL would false lock on a side lobe of the desired signal, a behavior which, as noted above, has been observed at times with WAAS reference receivers in Alaska. Such conditions are characterized by a constant output frequency error together with a low discriminator error signal, thus making this frequency error unobservable to the PLL. These simulation results led to a prototype implementation of the D-PLL algorithm using the current WAAS reference receiver developed by NovAtel. The firmware implemented D-PLL tracking for L1 C/A as well as an option for L2 P(Y) where this functionality can be disabled or coupled with L1 C/A operation. The performance of this prototype implementation has been successfully demonstrated at Zeta with test scenarios for RF interference, multipath, and phase scintillation. Additionally, field tests were performed in the Fall of 2008 at the Kotzebue, Alaska National Satellite Test Bed station. This station is located within the Arctic Circle and experiences phase scintillation conditions on a frequent basis. This test bed station also is adjacent to an operational WAAS reference station which allowed direct comparison of performance between this D-PLL prototype implementation and current WAAS tracking. This paper will document the simulation results, laboratory testing and these field test observations. It is anticipated this work will provide the basis for WAAS including this functionality in the reference receiver as a future product enhancement. More robust signal tracking at WAAS reference stations under a wider array of environmental conditions to include phase scintillation at northern latitude stations will have a net positive influence on service provided by WAAS. Additionally, WAAS has become a consistent source of high quality and high rate data for scientific purposes and providing improved tracking during increased solar activity further assists ionospheric research.
Published in:	Proceedings of the 2009 International Technical Meeting of The Institute of Navigation January 26 - 28, 2009 Disney's Paradise Pier Hotel Anaheim, CA
Pages:	924 - 936
Cite this article:	Shallberg, Karl, Morrissey, Tom, Grabowski, Joe, Olynik, Michael, "Dynamic Phase Lock Loop for Robust Receiver Carrier Phase Tracking," Proceedings of the 2009 International Technical Meeting of The Institute of Navigation, Anaheim, CA, January 2009, pp. 924-936.
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