Implementation and Analysis of an SDR Processor for GNSS Software Correlators

Götz Kappen, Volker Pieper, Lothar Kurz, Tobias G. Noll

Abstract:	This paper presents the design, implementation and quantitative analysis of processor architectures used in a Software Defined Radio (SDR) GNSS receiver. The various architectures are developed based on the concept of Application Specific Instruction Set Processors (ASIPs). Final goal of the ASIP GNSS SDR receiver is to overcome the efficiency vs. flexibility conflict and thus to use the smallest amount of silicon area and the lowest possible power consumption to enable the application of GNSS SDR receivers in mass-market, mobile, and battery powered equipment. Current research activity in the field of GNSS SDR receivers is summarized and demands, which have to be met by the processor architecture, are formulated. Compared to SDR approaches, where the software is optimized for a given hardware architecture (i.e. DSP, general purpose processor) this paper describes the co-design process of the GNSS SDR ASIP hardware and software to achieve maximum area and energy efficiency. In a first step a RISC based ASIP, which has been extended with special instructions, has been implemented and allows real-time processing of up to 3 channels at a processor clock frequency of 125 MHz. Adding a Single Instruction Multiple Data (SIMD) unit to the ASIP increases the number of processed samples per clock cycle and enables real-time processing of 13 channels at a clock frequency of only 140 MHz. The design of a Very Long Instruction Word (VLIW) processor is capable to further improve the flexibility of the SDR ASIP. Performance values of the developed processors as well as the required hardware resources for an FPGA implementation of the ASIP are presented to show that a testbed implementation is possible. However, as the main goal is a silicon chip implementation of the developed GNSS SDR ASIP, area values for an implementation in a 180 nm and 90 nm TSMC standard cell technology are given. The shown concept is extendable with dedicated functional units like DCOs or a Floating Point Unit tightly coupled to the ASIP.
Published in:	Proceedings of the 21st International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2008) September 16 - 19, 2008 Savannah International Convention Center Savannah, GA
Pages:	2258 - 2267
Cite this article:	Kappen, Götz, Pieper, Volker, Kurz, Lothar, Noll, Tobias G., "Implementation and Analysis of an SDR Processor for GNSS Software Correlators," Proceedings of the 21st International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2008), Savannah, GA, September 2008, pp. 2258-2267.
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