A Novel Scheme and Modified Structure for Improved Software GPS Receiver

Chieh-Fu Chang, Ru-Muh Yang, Ming-Seng Kao, and Jyh-Ching Juang

Abstract:	When implementing a software GPS receiver (SGR), few bits ADC are usually selected to reduce the required computation and storage. In this paper, the performance degradation induced by few bits ADC is discussed and the improved structures called post-correlator phase compensation (PCPC) is proposed. The analysis of PCPC structure is provided based on digital approach. For 1-bit SGR, the improvement of magnitude of correlator output can be up to 1.5 dB. The results of PC-based 1-bit SGR verify the feasibility of the proposed structure at static mode and dynamic mode. Finally, a novel scheme generating a 1-bit virtual carrier table with selectable fine resolution is proposed. Under some condition, the virtual carrier table can be attained with very light computations and much less storage compared with traditional carrier tables.
Published in:	Proceedings of the 20th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2007) September 25 - 28, 2007 Fort Worth Convention Center Fort Worth, TX
Pages:	2813 - 2822
Cite this article:	Chang, Chieh-Fu, Yang, Ru-Muh, Kao, Ming-Seng, Juang, Jyh-Ching, "A Novel Scheme and Modified Structure for Improved Software GPS Receiver," Proceedings of the 20th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2007), Fort Worth, TX, September 2007, pp. 2813-2822.
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