The GATE Receiver - A Full-Scale Galileo/GPS Monitor Receiver

T. Lück, E. Göhler, M. Bodenbach, J. Winkel, F. Förster

Abstract:	For the purpose of pre Galileo system verification and testing, the Galileo Test Environment (GATE) is setup in the German Alps to reproduce a realistic test bed for the Galileo satellite navigation system. In fact, a complete miniature navigation system is built up consisting of a control, ground and pseudo-space segment. For system monitoring and testing a receiver is required, which is capable of processing all signals specified in the Galileo system specification. To prove interoperability and for reference purposes the receiver will also process Galileo and GPS signals on L1 in a common processing chain. This paper describes a modular receiver design, developed for the use as a user receiver as well as a system monitor receiver. Detailed results from performance tests will be presented. Up to three single band receivers with radio frequency frontend and base band processor occupy up to nine slots of the PXI framework to serve any of the Galileo radio frequency bands E5, E6 and L1. One base-band board and a front-end system consisting of two cPCI boards cover each frequency band. The front-end system consists of a digital signal conditioning board and an analog front-end board. As the base-band units are based on field programmable gate arrays (FPGA), the actual band specific functionality of the receiver is implemented in a HDL and uploaded to the system. This flexibility allows all base-band units to be designed identically. The three receiver front-ends similarly have an identical PCB-layout, which reduces costs. The digital signal conditioning boards are all identical. The analog front-end boards have identical PCB layout, but differ in the components fitted (filters, LO-frequencies). Receiving the whole E5 band (i.e. E5a and E5b) including the first side-lobe (71 MHz) through one front-end system is the single most challenging requirement on the front-end system. To fulfill the required amplitude and group delay flatness in the pass-band is very challenging. The very high bandwidth demands high performance components and a careful design. For the other two bands the bandwidth is more relaxed. All three front-ends have a low-IF architecture with a single analog mixer stage and different filter stages in the RF- and IF-domain, respectively. For the subsequent A/D-converter jitter is a major concern. The sampling clock must exhibit ultra low jitter in order to prevent degradation of the received signal. The digitized signal is converted to base-band using a digital I/Q down-converter, thus the data rate to the digital base-band board is halved and the input bit-width is doubled. The advantage is that the requirements on the clocking of the base-band board are relaxed. Selection of the band to serve is performed by software, which uploads the corresponding configuration file to the base band FPGA. Two gate arrays of the latest Virtex 4 family are used for the base band processing. They provide up to thirty channels with up to five correlators each, controlled by embedded micro controllers (IBM PowerPC). Thus the receiver supports 90 generic channels, 30 on each frequency. For AltBOC tracking two channels are slaved together resulting in a maximum of 15 AltBOC channels simultaneously. Both gate array and associated microcontroller can be configured independently within the same RF band allowing to track GPS and Galileo/GATE signals simultaneously on one base band board. Different tracking methods for BOC, Alt-BOC signals or combined in phase and quadrature phase signal tracking algorithms are also implemented. All base band boards use the same clock signal provided by a rear PXI backplane mounted oscillator. The oscillator module can be either a rubidium or a temperature compensated crystal oscillator (TCXO) module depending on the application and requirements. Making use of dedicated clock lines of the PXI backplane, the clock signal is distributed to all receivers providing coherent clocking of all processing modules. To synchronize the local clocks of all receivers, a specialized PXI line is used to distribute a central signal, which triggers the pseudo range measurement on all receiver boards. Using a dedicated eight-bit bus for PXI cross-slot communication and the PXI star trigger lines, the local clocks of all boards are synchronized to each other. Each receiver board is addressable through the PXI bus. The main controller of each board is embedded in a fourth FPGA, running a Linux operating system. This offers most flexibility and allows addressing and configuring the receiver using standard protocols as TCP/IP or even HTTP and XML. Detailed results with real GPS signals as well as simulated Galileo signals from the GATE transmitters will be presented, focusing on acquisition and tracking methods and performance for new Galileo signal structures.
Published in:	Proceedings of the 19th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2006) September 26 - 29, 2006 Fort Worth Convention Center Fort Worth, TX
Pages:	1011 - 1020
Cite this article:	Lück, T., Göhler, E., Bodenbach, M., Winkel, J., Förster, F., "The GATE Receiver - A Full-Scale Galileo/GPS Monitor Receiver," Proceedings of the 19th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2006), Fort Worth, TX, September 2006, pp. 1011-1020.
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