Fast Prototyping a GPS Receiver with an FPGA

J. M. Hill

Abstract:	This research considers new concepts in GPS receiver design with the ultimate goal of consolidating the Intermediate Frequency (IF) and baseband processing as well as the navigation solution solver for one or more receivers into a field programmable gate array (FPGA). The primary focus is the key techniques required for such integration. The second focus is the test-bed constructed to demonstrate these techniques. Our first goal is to be able to produce replica code phase information from a satellite. Researchers and students interested in GPS receiver design as well as developers of specialty GPS receivers for space applications will benefit from this research.
Published in:	Proceedings of IEEE/ION PLANS 2006 April 25 - 27, 2006 Loews Coronado Resort Hotel San Diego, CA
Pages:	0 - 0
Cite this article:	Hill, J. M., "Fast Prototyping a GPS Receiver with an FPGA," Proceedings of IEEE/ION PLANS 2006, San Diego, CA, April 2006, pp. 0-0.
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