NAVAJO GPS ASIC The Ultimate Single Chip Baseband

Geraint Ffoulkes-Jones, David Belton, Damian Nolan and Robert Frayling-Cork

Abstract:	Can a single GPS ASIC be designed which will meet the requirements for both a very high sensitivity indoor capable GPS receiver and a high dynamics fast acquisition receiver? This was the challenge faced by the Navajo design team from CEVA. This paper details the use of off the shelf IP (Intellectual Property) blocks to create a high performance GPS baseband ASIC suitable for the most demanding applications and how through a parallel development path the software was developed to allow the new ASIC to be tracking satellites within 6 days of receipt! The ASIC must be capable of performing at the extremes of GPS performance, indoor GPS or very high dynamic. With the indoor level receiver the challenge is to be able to acquire and track signals down to -185dBW (~16dBHz) [5][6]. Whilst the high dynamic application must be capable of acquiring a minimum of four satellites within three seconds from a cold start whilst accelerating at more than 50g [7]. The performance of two Navajo ASIC based OEM board products are described along with the corresponding real-world acquisition, tracking, navigation, TTFF, power, MIPS, etc, performance results for an assisted indoor system, and a cold start high dynamic (up to 100g, 1500m/s) system.
Published in:	Proceedings of the 17th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2004) September 21 - 24, 2004 Long Beach Convention Center Long Beach, CA
Pages:	1488 - 1500
Cite this article:	Ffoulkes-Jones, Geraint, Belton, David, Nolan, Damian, Frayling-Cork, Robert, "NAVAJO GPS ASIC The Ultimate Single Chip Baseband," Proceedings of the 17th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2004), Long Beach, CA, September 2004, pp. 1488-1500.
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