Real Time Block Processing Engine for Software GNSS Receivers

Sanjeev Gunawardena, Frank van Graas, and Andrey Soloviev

Abstract:	Block processing techniques have shown promise in enhancing the capabilities of future Global Navigation Satellite System (GNSS) receivers. This is especially true in the context of GNSS software-defined radios (SDR) where the processing algorithms can be designed to adapt to various applications, environmental conditions, and multiple GNSSs. To achieve real-time block processing, several large FFT operations must be performed within the pre-detection integration time. Few implementation platforms exist with this capability. To date, Application Specific Integrated Circuits (ASICs) have been the preferred platform. However, implementing a GNSS SDR in an inflexible ASIC defies its purpose. On the other hand, total software processing has been demonstrated, but is currently only possible for traditional serial processing techniques, and only when the sampling frequency is relatively low. In recent years, programmable logic technologies have advanced tremendously and are beginning to replace conventional ASICs in many applications. These devices offer the flexibility of software coupled with the performance benefits of custom designed hardware. Modern Field Programmable Gate Arrays (FPGAs) have densities on the order of several million system gates and can operate at relatively high clock frequencies (~400 MHz). Hence, FPGAs offer great opportunities for implementing real-time block processing GNSS SDRs. In this paper we describe a real time block processing engine that has been developed and implemented in FPGA technology. The engine performs the well known FFT-based circular convolution operation that yields correlation outputs for all possible replica code offsets at once. Currently, this operation can be performed in less than 15 microseconds, allowing the engine to be used multiple times during the one-millisecond GPS C/A code period for performing such operations as fast acquisition, weak signal acquisition, and SV anomalous event monitoring. This paper is organized as follows: the introduction describes the two main techniques used for block processing, the complementary nature of time versus frequency domain GNSS signal processing, and the rationale for a joint time-frequency receiver. The averaging method used to reduce the FFT size is described. Next, the hardware architecture and implementation details of the block-serial receiver are presented. The paper concludes with the performance and features realized with the current version of the receiver that was successfully implemented.
Published in:	Proceedings of the 2004 National Technical Meeting of The Institute of Navigation January 26 - 28, 2004 The Catamaran Resort Hotel San Diego, CA
Pages:	371 - 377
Cite this article:	Gunawardena, Sanjeev, van Graas, Frank, Soloviev, Andrey, "Real Time Block Processing Engine for Software GNSS Receivers," Proceedings of the 2004 National Technical Meeting of The Institute of Navigation, San Diego, CA, January 2004, pp. 371-377.
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