A Low Power GPS Chipset with Scalable Performance and Open Architecture for Modern Location Aware Systems

M. Cavadini, P. Young, J. Brenner, F. Piazza

Abstract:	A scalable low power GPS chip set is presented that covers the needs of a GPS sensor up to the one of a microprocessor with GPS functionalities. The chip set architecture offers several configuration options in terms of system clocking strategies, power supplies and external component selection and consumes less than 25mW in 1 fix per second situation. The paper focuses on the hardware components and their characteristics for low power consumption.
Published in:	Proceedings of the 16th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS/GNSS 2003) September 9 - 12, 2003 Oregon Convention Center Portland, OR
Pages:	700 - 705
Cite this article:	Cavadini, M., Young, P., Brenner, J., Piazza, F., "A Low Power GPS Chipset with Scalable Performance and Open Architecture for Modern Location Aware Systems," Proceedings of the 16th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS/GNSS 2003), Portland, OR, September 2003, pp. 700-705.
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