Highly Integrated Chipset for GPS Receivers Using RISC,

Peter M. Bingham and Martin Fryer

Abstract:	This paper describes the implementation of a very highly integrated chipset for Global Positioning System Receivers for high performance at low cost. The products described include a CMOS multi- channel correlator and a 32-bit RISC Processor (ARM60) for GPS signal processing. The use of these parts, with a silicon integrated RF downconverter (or front end) GPlOlO, can form the basis of a low cost GPS chipset. Future trends in the development of GPS receiver technology are also discussed for commercial applications,
Published in:	Proceedings of the 6th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1993) September 22 - 24, 1993 Salt Palace Convention Center Salt Lake City, UT
Pages:	929 - 938
Cite this article:	Bingham, Peter M., Fryer, Martin, "Highly Integrated Chipset for GPS Receivers Using RISC,," Proceedings of the 6th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1993), Salt Lake City, UT, September 1993, pp. 929-938.
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