Abstract: | Early GPS Systems were developed in the era of Small Scale Integration (SSI), and, in common with other electronic systems, have been reduced in cost, size and power consumption, by increasing the level of integration. For example, Navstar Systems original XR1 was implemented with extensive analogue circuits, XR3 integrated a single channel, and XR5 put 6 such channels onto a single chip. This paper describes the current State of the Art of GPS integration, as implemented in the XR7 Chipset. A GPS System requires an r.f. front end, multi-channel downconvert-decoder hardware, and a microprocessor together with memory and other support chips. The potential now exists for most of these to be integrated, although the problems of co-locating r.f and digital, and the cost of memory, mitigates against the ultimate single chip solution. However, integration does not have to stop at the GPS sub-system, but can extend into the application functions. For example, Symmetricom Inc. itself manufactures a range of timing equipment for the telecoms industry. Many of the key peripherals required for this type of equipment can be integrated together with the GPS System onto a single chip, giving a performance cost, and size, benefit. The objective behind the development of the XR7 Chip Set was to achieve the maximum cost-effective level of integration. This paper describes the development of this new XR7 GPS Chip Set. The Digital ASIC (or XR7 GPS Microcontroller) incorporates a 12-channel GPS DSP, ARM7TDMIÔ micro-processor, memory, analogue devices, RTC, UARTs, timing and communication peripherals, all on one chip. Together with the companion XR7 RF front end chip these functions allow a complete GPS Sensor to be created with the use of just the two chips, plus memory. Key integrated peripherals are also described in the paper, particularly specific support for timing and synchronization applications. Other integrated peripherals such as the communication modules, flexible I/O, analogue functions and event counters provide simple and flexible interfaces to other sub-systems. The paper also introduces the first systems which are being developed around this GPS chipset, utilizing the integrated application peripherals, including a minimal implementation in 1 1 /2 x 2 1 /4 inch format, and a telecoms reference clock. |
Published in: |
Proceedings of the 12th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1999) September 14 - 17, 1999 Nashville, TN |
Pages: | 1043 - 1052 |
Cite this article: | Anderson, Peter, Bickerstaff, Jacqueline, "Symmetricom XR7 GPS Chip Set With Built In Application Peripherals," Proceedings of the 12th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1999), Nashville, TN, September 1999, pp. 1043-1052. |
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