SiRFstarI/LX Low Power GPS Architecture

Greg Turetzky, Jerry Knight, Chuck Norman

Abstract:	The SiRFStar1/LX GPS architecture represents the latest advances in silicon and software technology to enable extremely low power operation without sacrificing track-ing or navigation performance. It builds upon the fast search capabilities of the original GSP1 and incorporates new silicon processes to reduce power requirements such that the chipset can run at 3V. These features will enable the chipset to help move GPS into new arenas in con-sumer electronics where power consumption is a critical performance measure. The GSP1/LX employs 3 V CMOS technology and inno-vative circuit designs to minimize power consumption. An accurate, low power internal clock allows the receiver to power down between measurements. The fast search capability of the chipset allows the receiver to reacquire and resume measurements on all 12 channels within 100 ms. For continuous 1Hz measurements, a net power re-duction (compared to the previous generation) of over 93% is achieved. Further reductions to over 98% can be obtained when the receiver wakes only to compute a fix on demand. This paper will describe the hardware and software im-plemented to achieve these results and presents test re-sults.
Published in:	Proceedings of the 10th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1997) September 16 - 19, 1997 Kansas City, MO
Pages:	75 - 79
Cite this article:	Turetzky, Greg, Knight, Jerry, Norman, Chuck, "SiRFstarI/LX Low Power GPS Architecture," Proceedings of the 10th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 1997), Kansas City, MO, September 1997, pp. 75-79.
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