Design and Implementation of the Discrete-Update Frequency-Locked Loop

Ryan S. Cassel

Peer Reviewed

Abstract:	Frequency-locked loops (FLLs) are important in many signal processing applications, including communications and satellite navigation. Direct design of the discrete-update FLL (DFLL) in the digital domain is outlined herein and offers many advantages over the discretization of analog design, including the ability to better control the loop bandwidth and damping. The transfer functions, loop bandwidths, and loop constants that describe the DFLL are derived, and an iterative algorithm for computing the loop constants based on the desired loop bandwidth and update interval is provided. Theoretical performance is examined in terms of steady-state tracking error, random errors due to noise, and expected signal-to-noise ratio (SNR) losses due to tracking errors. The theory is supported through simulation, and the tradeoff between noise suppression and dynamic performance is highlighted. It is shown that using the DFLL constants derived in this paper is critical in ensuring that actual DFLL performance can be accurately predicted and controlled.
Published in:	Proceedings of the 34th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2021) September 20 - 24, 2021 Union Station Hotel St. Louis, Missouri
Pages:	3783 - 3803
Cite this article:	Cassel, Ryan S., "Design and Implementation of the Discrete-Update Frequency-Locked Loop," Proceedings of the 34th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2021), St. Louis, Missouri, September 2021, pp. 3783-3803. https://doi.org/10.33012/2021.18002
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