Exploring the Chip Scale Atomic Clock Within a GPS Disciplined Oscillator

Luke Littleton-Strand, Filip Nedelkov, Erin Griggs, Dennis Akos

Peer Reviewed

Abstract: GPS Disciplined Oscillators (GPSDOs) are prevalent and accurate systems for timekeeping that can be used in GPS navigation applications. They work by combining the long-term stability of GPS timekeeping with the short-term stability of a quartz or atomic oscillator. Timekeeping is a critical element to navigation in GPS-based systems and can be improved by using a more accurate Chip Scale Atomic Clock (CSAC), as compared to a Temperature Compensated Crystal Oscillator (TCXO). The stability of the CSAC is also essential in environments where GPS signals are degraded or unreliable, such as in GPS-spoofed or GPS-denied environments. This paper aims to characterize the CSAC’s ability as a timekeeping source in these environments where a GPS receiver cannot deliver reliable timing solutions. This paper aims to study a GPSDO system comprised of the Microsemi SA.45s CSAC and a Ublox ZED-F9T high accuracy timing module. The ZED-F9T is a multiband GNSS receiver that can deliver 8 ns time mark resolution and a 4 ns time-pulse jitter [1]. The ZED-F9T will be the source of the 1 Pulse Per Second (1PPS) used in this paper. The CSAC can deliver a short-term Allan Deviation of 3 × 10!"" (? = 100s) and 1 × 10!"" (? = 1000s) [2]. The CSAC offers a variety of operational modes; however, this paper will focus on the 1PPS Phase Measurement Mode and the 1PPS Disciplining Mode. In the Phase Measurement Mode, the CSAC reports the phase difference between the external 1PPS input and the 1PPS output with a 100ns resolution. In 1PPS Disciplining Mode, the CSAC measures the difference in phase between the externally provided 1PPS and the outgoing 1PPS. This value is then provided asinput for an internal algorithm that controls the microwave synthesizer in the physics package. The algorithm steers the frequency and the 1PPS output to that of the provided input 1PPS signal. When the 1PPS input is lost while operating in Disciplining Mode, the CSAC enters a holdover state. All CSACs have errors in their operation due to both internal and environmental factors [2]. The purpose of this paper is to model and characterize these errors so that the CSAC can be effectively and accurately used in a variety of environments and operating modes. The paper will study the CSAC’s behavior in the Disciplining Mode while being actively disciplined and will study the Phase Measurement Mode. The use of the Disciplining Mode models situations in which the CSAC is operated in areas with GPS signals, and the operation of the CSAC in Phase Measurement Mode reflects the operation when the CSAC cannot be externally disciplined. Additionally, the CSAC will be compared with two other common types of oscillators: two TCXOs and a Rubidium Frequency Standard. These oscillators will be compared within the context of a software-defined radio (SDR)-based GPS receiver. This research is novel in that it focuses on the use of the CSAC in environments where GPS signal integrity is in question and unreliable. The paper attempts to specifically characterize the CSAC's drift in holdover modes and measurement modes where the 1PPS input signal is not usable.
Published in: Proceedings of the 2021 International Technical Meeting of The Institute of Navigation
January 25 - 28, 2021
Pages: 254 - 268
Cite this article: Littleton-Strand, Luke, Nedelkov, Filip, Griggs, Erin, Akos, Dennis, "Exploring the Chip Scale Atomic Clock Within a GPS Disciplined Oscillator," Proceedings of the 2021 International Technical Meeting of The Institute of Navigation, January 2021, pp. 254-268. https://doi.org/10.33012/2021.17831
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