Engineering a GPS Receiver for Lowest Power Consumption

Francesco Piazza, Marco Cavadini, Alfredo Knecht and Jim Bruister

Abstract:	In this work the essential elements of a complete low power GPS receiver targeting portable devices are presented. These building blocks comprise a Low Noise Amplifier (LNA), a radio frequency front-end, a base band processor and a low-level software stack. The achievable reduction in power consumption with respect to currently available solutions is of a factor 3 to 20. After reviewing the challenges faced by a receiver manufacturer planning for the next generation of GPS applications, the TChip approach for low power at both system and device level is presented. The implementation of the single receivers elements is presented, and results based on simulated as well as measured performance are discussed. Lastly, a hardware software co-design platform allowing for fast application prototyping, system-on-a-chip development and real-time receiver characterization is presented.
Published in:	Proceedings of the 14th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 2001) September 11 - 14, 2001 Salt Palace Convention Center Salt Lake City, UT
Pages:	835 - 843
Cite this article:	Piazza, Francesco, Cavadini, Marco, Knecht, Alfredo, Bruister, Jim, "Engineering a GPS Receiver for Lowest Power Consumption," Proceedings of the 14th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 2001), Salt Lake City, UT, September 2001, pp. 835-843.
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