On Implementing GPS Block Processing Techniques in Fixed-Point Programmable Hardware

Sanjeev Gunawardena and Frank van Graas

Abstract:	Block processing techniques have shown promise in enhancing the capabilities of GPS receivers. To achieve real-time block processing, several large forward and inverse Fast Fourier Transforms (FFT/IFFTs) must be performed within the pre-detection integration time. Few implementation platforms exist with this capability. To date, Application Specific Integrated Circuits (ASICs) have been the preferred solution in terms of speed. However, the implementation of a GPS Software-Defined Radio (SDR) in an inflexible ASIC defies its purpose. In recent years, programmable logic technologies have advanced tremendously and are beginning to replace conventional ASICs in many applications. Since they are programmable, these devices offer the flexibility of software coupled with the performance benefits of custom designed hardware. Modern Field Programmable Gate Arrays (FPGAs) have densities on the order of several million system gates and can operate at relatively high clock frequencies (~300 MHz). Hence, FPGAs offer great opportunities for a block processing GPS SDR. When migrating the double-precision block processing algorithms developed in software to a fixed-point hardware realization such as for an FPGA, it is important to consider the performance degradation due to finite precision effects. Moreover, since each extra bit of precision in hardware translates to an exponential growth in chip area, and hence complexity, power dissipation, and cost, determining the minimum required bit-precision early in the design cycle is crucial. Even though the fixed-point error bound for the FFT is well documented, its direct application to the GPS blockprocessing problem is difficult to analyze in closed-form. This paper presents statistical results of fixed-point block processing simulations performed exactly as in hardware with real GPS data. In order to quantify the performance degradation compared to a double-precision software implementation (considered as the truth), several performance parameters were defined. The results show the degradation in performance for every major processing stage from the analog-to-digital converter (ADC) to the FFT/IFFT pipeline, and for such receiver functions as acquisition and pseudorange measurement. Simulation results are shown for precisions ranging from two to twelve-bits. The results presented in this paper can be used to estimate the optimal fixed-point precisions needed at the various stages of a GPS block processing SDR implemented in programmable hardware for a given application.
Published in:	Proceedings of the 14th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 2001) September 11 - 14, 2001 Salt Palace Convention Center Salt Lake City, UT
Pages:	778 - 788
Cite this article:	Gunawardena, Sanjeev, van Graas, Frank, "On Implementing GPS Block Processing Techniques in Fixed-Point Programmable Hardware," Proceedings of the 14th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GPS 2001), Salt Lake City, UT, September 2001, pp. 778-788.
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