High-g Capacitive Accelerometer Arrays with Low Bias Instability

Gary K. Fedder, Vincent P.J. Chung, Metin G. Guney, Xiaoliang Li, Yi Chung Lin, Suresh Santhanam, Jeyanandh Paramesh, Tamal Mukherjee

Abstract: Accelerometer metrics of performance include higher dynamic range, lower noise, lower bias instability and lower power. As with all systems, these trade-offs compete. Achieving large dynamic range in accelerometers drives design trade-offs of sensitivity and survivability at the high end and low noise and drift at the low end of the range. CMOS-MEMS technology enables deployment of system-on-chip designs comprising an array of hundreds of individual accelerometer cells integrated with low-noise readout circuits and on-chip temperature, stress, and scale-factor sensors to compensate drift. These systems range to 50 kg shock measurement with 3 mg bias instability and a path toward micro-g bias instability.
Published in: 2020 IEEE/ION Position, Location and Navigation Symposium (PLANS)
April 20 - 23, 2020
Hilton Portland Downtown
Portland, Oregon
Pages: 9 - 15
Cite this article: Fedder, Gary K., Chung, Vincent P.J., Guney, Metin G., Li, Xiaoliang, Lin, Yi Chung, Santhanam, Suresh, Paramesh, Jeyanandh, Mukherjee, Tamal, "High-g Capacitive Accelerometer Arrays with Low Bias Instability," 2020 IEEE/ION Position, Location and Navigation Symposium (PLANS), Portland, Oregon, April 2020, pp. 9-15.
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