|Abstract:||A highly integrated dual-channel RF front-end Integrated Circuit (IC) with its architecture, simulation, and first measurement results of the manufactured chip on an evaluation board are presented. The “PASCAL” IC enables simultaneous reception of two independently configurable channels with up to 60 MHz bandwidth anywhere in the GNSS L-band range. Both channels use a lowintermediate frequency (IF) architecture. The IC was implemented in a Globalfoundries 55 nm CMOS process technology and has a die size of 1.88 mm x 1.70 mm. The IC is packaged in a 6 mm x 6 mm QFN48 housing with exposed paddle. All manufacturing process variations which are required by the foundry have been considered and are fulfilled. The front-end has been designed to achieve low power consumption and to reduce the front-end’s area within the whole GNSS receiver. The measured core current consumption of the front-end with a 4 bit Analog to Digital Converter (ADC) configuration is 80.0 mA for both channels activated with a 1.2 V supply voltage with an external LOs (1544 MHz and 1248 MHz) and ADC clock (250 MHz). Using this configuration, the front-end demonstrated a functional E1/E6 Pseudo-PRS receiver. The digital interface pads require a 1.8 V supply. Different power saving modes are supported that will be detailed in the paper.|
Proceedings of the 32nd International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2019)
September 16 - 20, 2019
Hyatt Regency Miami
|Pages:||246 - 255|
|Cite this article:||
Urquijo, Santiago, Rügamer, Alexander, Milosiu, Heinrich, Felber, Wolfgang, "A Highly Integrated Dual-channel Configurable GNSS Receiver Front-end for Wideband Reception," Proceedings of the 32nd International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2019), Miami, Florida, September 2019, pp. 246-255.
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