Title: Quantifying Phase Lock Loop Robustness Through Interference using the Phase Discriminator Output
Author(s): Wengxiang Zhao, Stefan Stevanovic, Boris Pervan
Published in: Proceedings of IEEE/ION PLANS 2018
April 23 - 26, 2018
Hyatt Regency Hotel
Monterey, CA
Pages: 56 - 62
Cite this article: Zhao, Wengxiang, Stevanovic, Stefan, Pervan, Boris, "Quantifying Phase Lock Loop Robustness Through Interference using the Phase Discriminator Output," Proceedings of IEEE/ION PLANS 2018, Monterey, CA, April 2018, pp. 56-62.
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Abstract: In this paper, we develop a PLL performance measure that allows phase lock loop design parameters to be determined given a mean time to cycle slip requirement. This concept is directly applicable to both stationary and moving GPS receivers subject to wideband radio frequency interference. The PLL performance metric developed in [1] is improved to rule-out inadequate PLL designs and allow time-consuming experimental validation to be reserved for designs that that much more likely to be successful. This is accomplished by using direct non-linear PLL simulation to quantify the relationship between the discriminator output standard deviation and the mean time to cycle slip. This relationship can then be used to determine a suitable threshold for the DO standard deviation given a mean time to cycle slip requirement, which will depend on the particular application of interest. Then the phase lock loop parameters that are necessary to achieve this mean time to cycle slip can be determined analytically. Additional simulation results show that DO standard deviations less than 52 degrees correspond to more favorable DO distributions, and this translates to longer mean time to cycle slip. In addition, our results further validate the DO metric by showing that increasing coherent averaging time is the only way to obtain substantial increases in mean time to cycle slip under interference conditions.