|Abstract:||The objective of this work is to enable the implementation of several computationally expensive, sophisticated Global Navigation Satellite System (GNSS) signal processing algorithms in real-time receivers. Detailed design of coprocessor digital hardware that handles all the receiver data path computations succeeding the digitized intermediate frequency (IF) sample generation leading up to the navigation solution computation, is presented. The data path computations of the co-processor include signal correlation, acquisition metric generation, code and carrier tracking loops, data bit synchronization, code and carrier measurement generation, and navigation data decoding. The proposed co-processor exposes all the critical design parameters and allows itself to be programmed from an external processing unit thus maintaining the design flexibility. In addition, the proposed co-processor core is fundamentally independent of the GNSS signal type it is programmed to process, and this feature enables the receiver designer to deploy multiple co-processors to design a multi-GNSS receiver. Thus the proposed coprocessor aims to meet the objective by substantial acceleration of time critical computations, thereby creating opportunities for further exploration of real-time GNSS receiver performance enhancement.|
Proceedings of the 30th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2017)
September 25 - 29, 2017
Oregon Convention Center
|Pages:||3584 - 3592|
|Cite this article:||
Shivaramaiah, Nagaraj C., Akos, Dennis M., "A Correlation, Measurement and Data Decoding Co-processor for Multi-GNSS Receivers," Proceedings of the 30th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2017), Portland, Oregon, September 2017, pp. 3584-3592.
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