The Chip-Scale Atomic Clock - Low-Power Physics Package

R. Lutwak, J. Deng, W. Riley, M. Varghese, J. Leblanc, G. Tepolt, M. Mescher, D. K. Serkland, K. M. Geib, G. M. Peake

Abstract: We have undertaken a development effort to produce a prototype chip-scale atomic clock (CSAC). The design goals include short-term stability, 10 1 / 2 y ( ) 6 10- - s t < × t , with a total power consumption of less than 30 mW and overall device volume < 1 cm3. The stringent power requirement dominates the physics package architecture, necessarily dictating a small (< 1 mm3) volume gaseous atomic ensemble interrogated by a low-power semiconductor laser. At PTTI 2002 and PTTI 2003, we reported on laboratory experiments that underlie the fundamental architecture of our CSAC, based on interrogation of the cesium D1 transition by the technique of coherent population trapping (CPT). In the past year, the development effort has shifted from fundamental research and feasibility investigation to engineering and prototype development. In this paper, we report on the design of a rugged and compact physics package that is expected to exceed the ultimate performance and power requirements of the CSAC.
Published in: Proceedings of the 36th Annual Precise Time and Time Interval Systems and Applications Meeting
December 7 - 9, 2004
Hyatt Regency Washington on Capitol Hill
Washington, D.C.
Pages: 339 - 354
Cite this article: Lutwak, R., Deng, J., Riley, W., Varghese, M., Leblanc, J., Tepolt, G., Mescher, M., Serkland, D. K., Geib, K. M., Peake, G. M., "The Chip-Scale Atomic Clock - Low-Power Physics Package," Proceedings of the 36th Annual Precise Time and Time Interval Systems and Applications Meeting, Washington, D.C., December 2004, pp. 339-354.
Full Paper: ION Members/Non-Members: 1 Download Credit
Sign In