A Fast Low-Energy Acquisition Technology For GPS Receivers

Daniel Harrison, Naresh Rao, Donald McGrath, Paul Frank, Nga Lee, and Jerome Tiemann

Abstract:	We have developed a high-speed, low-power, parallel-correlation technique that dramatically reduces GPS signal-acquisition time and energy. For example, a brute-force search over 2046 code-offset positions for 24 satellite codes in 13 frequency bins consumes only 0.065 Joules and takes only 0.68 seconds. This is very important for battery-powered applications and for rapid direct acquisition of the military P(Y) GPS signals in a jamming environment. The dramatic time reduction is achieved by storing a short acquisition-signal segment in a digital memory and then rapidly searching this stored segment for all desired GPS signals. Ultra-low energy consumption is achieved by reducing the receiver “on” time, and by using a novel and extremely efficient parallel-correlator architecture. In the following sections, we describe the new correlator technique, the architecture of the fabricated prototype IC, and conclude with preliminary IC-testing results.
Published in:	Proceedings of the 55th Annual Meeting of The Institute of Navigation (1999) June 27 - 30, 1999 Royal Sonesta Hotel Cambridge, MA
Pages:	433 - 441
Cite this article:	Harrison, Daniel, Rao, Naresh, McGrath, Donald, Frank, Paul, Lee, Nga, Tiemann, Jerome, "A Fast Low-Energy Acquisition Technology For GPS Receivers," Proceedings of the 55th Annual Meeting of The Institute of Navigation (1999), Cambridge, MA, June 1999, pp. 433-441.
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