Software-Defined GPS Receiver Implemented on the Parallella-16 Board

Daniel Olesen, Jakob Jakobsen, Per Knudsen

Peer Reviewed

Abstract:	This paper describes a GPS software receiver design made of inexpensive and physically small hardware components. The small embedded platform, known as the Parallella-16 computer has been utilized in conjunction with a commercial RF front-end to construct a 4-channel real time software GPS receiver. The Parallella-16 board is a kickstarter-funded platform consisting of a dual-core ARM A9 CPU, an integrated FPGA and a 16-core coprocessor known as the Epiphany. The main contribution in this paper has been the development of a GPS tracking algorithm, which utilizes the parallelism in the Epiphany processor. The total cost of the hardware is below 150$ and the size is comparable to a credit-card. The receiver has been developed for research in GNSS/INS integration on small Unmanned Aerial Vehicles (UAVs).
Published in:	Proceedings of the 28th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2015) September 14 - 18, 2015 Tampa Convention Center Tampa, Florida
Pages:	3171 - 3177
Cite this article:	Olesen, Daniel, Jakobsen, Jakob, Knudsen, Per, "Software-Defined GPS Receiver Implemented on the Parallella-16 Board," Proceedings of the 28th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2015), Tampa, Florida, September 2015, pp. 3171-3177.
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