NAPA: A Fully Integrated Multi-constellation Two-frequency Single-chip GNSS Receiver

F. Garzia, S. Köhler, S. Urquijo, P. Neumaier, J. Driesen, S. Haas, T. Leineweber, T. Zhang, S. Krause, F. Henkel, A. Rügamer, M. Overbeck, G. Rohmer

Abstract:	This paper presents the overall architecture, the implementation, test setup, and first measurements results of a fully integrated multi-constellation two-frequency single-chip GNSS receiver. The ASIC supports the simultaneous reception and processing of the GPS L1/L5, Galileo E1/E5a and GLONASS G1 signals with 40 versatile tracking channels. The dual-band analog RF front-end is integrated on the same mixed-signal chip as the baseband hardware including an embedded LEON2 processor to close the tracking loops. The chip was realized in a low-power 1.2 V 65nm TSMC technology.
Published in:	Proceedings of IEEE/ION PLANS 2014 May 5 - 8, 2014 Hyatt Regency Hotel Monterey, CA
Pages:	1075 - 1083
Cite this article:	Garzia, F., Köhler, S., Urquijo, S., Neumaier, P., Driesen, J., Haas, S., Leineweber, T., Zhang, T., Krause, S., Henkel, F., Rügamer, A., Overbeck, M., Rohmer, G., "NAPA: A Fully Integrated Multi-constellation Two-frequency Single-chip GNSS Receiver," Proceedings of IEEE/ION PLANS 2014, Monterey, CA, May 2014, pp. 1075-1083. https://doi.org/10.1109/PLANS.2014.6851476
Full Paper:	ION Members/Non-Members: 1 Download Credit Sign In