Feasibility Study on the Use of Xilinx COTS Radiation Hardened FPGA to Implement GNSS Signal Acquisition for Space Applications

S. Ramakrishnan, P. Enge

Abstract:	Software Defined Receivers (SDRs) for GNSS signals have evolved greatly over the past two decades. Originally conceived to run on a general purpose processor, SDRs today have also been implemented on Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) and Graphical Processing Unit (GPU). Thanks to Moore’s Law, real-time multi-channel GNSS receivers are realizable on any of the stated computation units. SDRs provide for a reconfigurable open-architecture receiver enabling dynamic selection of parameters tailored to the needs of the application. An open architecture GNSS receiver is of particular interest for use in space missions. Applications for GNSS in space include on-board orbit determination and attitude solutions, guidance system for crewed vehicles, formation flying and tracking and control of communication satellite constellations. Significant challenges to the use of GNSS receivers in space include limited GNSS satellite visibility, weak signal reception and high Doppler rates. The possibility of electronic components being exposed to ionizing radiation while in space creates special design challenges. Electronic components must be radiation-hardened (rad-hard) to ensure its continued operation in space. The limited market size and manufacturing complexities make rad-hard products expensive. Further, space grade technology can be several generations older compared to its commercial cousins. Consequently, the diminished computational capabilities of space grade rad-hard general purpose processors and FPGA is a hindrance that must be dealt with. The NASA Goddard Space Flight Center has been actively pursuing the development of reconfigurable GPS receivers designed specifically for space missions. The Navigator GPS Receiver uses Commercial Off-The-Shelf (COTS) FPGA to implement specialized fast acquisition module. FPGA rather than Application-Specific Integrated Circuits (ASIC) were chosen to maintain flexibility for growth and design modification. This paper is a feasibility study on the possibility of further enhancing the processing capabilities of the Navigator GPS Receiver. The first objective of this paper is to evaluate the suitability of Xilinx COTS space grade FPGA to implement a GPS L1C/A receiver. In particular, two chips from the Virtex-4QV and Virtex-5QV families are to our interest. The specific chips are XQR4VFX140 and XQR5VFX130 respectively. The Virtex-4QV chip has lower radiation tolerance but included within are two embedded PowerPC processors. The Virtex-5QV chip has greater tolerance, enhanced signal processing capabilities and lower power consumption. It does not include an embedded processor. Based off information in the literature, the Navigator GPS Receiver uses three Actel RTAX2000 FPGAs in its design. Two of the three FPGAs are used to implement the acquisition module. This module is designed as a parallel code phase FFT search using a sampling rate of 2.048 Mega-samples per second (Msps). Consequently, the design uses a simple Radix-2 2048 point FFT architecture. An identical implementation was mapped onto the two Xilinx FPGA chips under study. Simulated data are used in evaluating the accuracy of the results. Preliminary routing results indicate both devices can support a GPS L1 C/A acquisition module on a single device with sufficient resources to spare for other modules. Further, the FFT engine can run at least 4x faster compared to the Actel implementation. The second objective of this paper is to evaluate the capabilities of the two Xilinx chips to support acquisition of the GPS L1 Composite or Galileo E1 Composite signal. The ability to acquire and track this common signal from both constellations will guarantee at least four satellites are always tracked at Geostationary Orbits with a C/No threshold of 25 dB-Hz. Acquiring the L1C signal would require support for a 65536 point FFT. The FFT is implemented using a Radix-4 butterfly structure. Preliminary results indicate that both Xilinx devices can support a 65536 point FFT/IFFT albeit at significantly higher resource utilization. In particular, high utilization is observed for the dedicated DSP slices and Block RAMs used to implement the butterfly structure. Over 95% of the computational logic blocks are still unused. These CLBs can be used to implement other modules within the same single chip. The third objective of this paper is to evaluate the Xilinx TMRTool. This tool automates the inclusion of redundancy into the design to prevent Single Event Upsets (SEUs) and Single Event Transients (SETs). Redundancy is a logical technique to rad-hard devices at the circuit level. Voting logic is used to identify and isolate erroneous results. The tool allows the user to control which portion of the implementation logic should include redundancy. Optimizing the design to lower resource utilization without loss of redundancy would be explored.
Published in:	Proceedings of the 26th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2013) September 16 - 20, 2013 Nashville Convention Center, Nashville, Tennessee Nashville, TN
Pages:	1527 - 1538
Cite this article:	Ramakrishnan, S., Enge, P., "Feasibility Study on the Use of Xilinx COTS Radiation Hardened FPGA to Implement GNSS Signal Acquisition for Space Applications," Proceedings of the 26th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS+ 2013), Nashville, TN, September 2013, pp. 1527-1538.
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