The Chip-Scale Atomic Clock - Prototype Evaluation

R. Lutwak, A. Rashed, M. Varghese, G. Tepolt, J. LeBlanc, M. Mescher, D. K. Serkland, K. M. Geib, G. M. Peake, and S. Römisch

Abstract:	The authors have developed a chip-scale atomic clock (CSAC) for applications requiring atomic timing accuracy in portable battery-powered applications. At PTTI/FCS 2005, we reported on the demonstration of a prototype CSAC, with an overall size of 10 cm3, power consumption ˜150 mW, and short-term stability sy(t)***1x10^-9t^-1/2. . Since that report, we have completed the development of the CSAC, including provision for autonomous lock acquisition and a calibrated output at 10.0 MHz, in addition to modifications to the physics package and system architecture to improve performance and manufacturability. Ten pre-production CSACs have been constructed in order to test unit-to-unit performance variations and to gain statistical confidence in operating specifications, environmental sensitivity, and manufacturability. All of the units have been subjected to a standard set of performance tests. Several of the units have been distributed to DoD system integrators and external testing facilities. Others have been subjected to environmental testing, including shock and vibration, long-term aging, and temperature performance. This paper will review the CSAC architecture, with particular attention to those aspects which have evolved since our previous report, as well as the results of evaluation of the preproduction CSACs.
Published in:	Proceedings of the 39th Annual Precise Time and Time Interval Meeting November 27 - 29, 2007 Hyatt Regency Long Beach Long Beach, California
Pages:	269 - 290
Cite this article:	Lutwak, R., Rashed, A., Varghese, M., Tepolt, G., LeBlanc, J., Mescher, M., Serkland, D. K., Geib, K. M., Peake, G. M., Römisch, S., "The Chip-Scale Atomic Clock - Prototype Evaluation," Proceedings of the 39th Annual Precise Time and Time Interval Meeting, Long Beach, California, November 2007, pp. 269-290.
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