Performance Analysis of the FPGA-based Software Defined GPS Receiver

Ya-Tzu Chen and Shau-Shiun Jan

Abstract:	A field-programmable gate array (FPGA) offers the possibility of high parallelism, speed comparable to an ASIC, a large number of input/output (I/O), re-programmability, and a great deal of design flexibility. For the reason, a real-time GPS software-defined radio (SDR) receiver based on FPGA technology is being in great demand because of its practicality as both a testing device and a final product. In this paper, a real-time FPGA-based GPS SDR receiver is developed to support the GNSS augmentation system projects. All the procedures for the design and the performance analysis of a FPGA-based GPS SDR receiver are presented in detail. In this work, a FPGA board manufactured by Xilinx is chosen as an example, and it collaborates with the Xilinx ISE design tool to develop a FPGA-based GPS SDR receiver. The other branch of this work breaks into the performance analysis of the developed GPS SDR under multipath environments which is evaluated with modified baseband architecture. As for the multipath issue, this paper changes the correlator architecture to reduce the multipath effects. According to the results of the performance analyses, the proper algorithms for multipath environment could be evaluated effectively. Accordingly, this paper could be served as a tutorial for users could learn and build their FPGA-based GPS SDR with the similar software and hardware.
Published in:	Proceedings of the 25th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2012) September 17 - 21, 2012 Nashville Convention Center, Nashville, Tennessee Nashville, TN
Pages:	2326 - 2332
Cite this article:	Chen, Ya-Tzu, Jan, Shau-Shiun, "Performance Analysis of the FPGA-based Software Defined GPS Receiver," Proceedings of the 25th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2012), Nashville, TN, September 2012, pp. 2326-2332.
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