Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy

Benjamin Z. Tang, Stephen Longfield, Jr., Sunil A. Bhave, Rajit Manohar

Abstract:	High power consumption of existing GPS receiver chips limits continuous GPS operation in mobile devices. In order to pave the way for advances in areas such as location-aware applications and micro robotics navigation, we have to reduce the power consumed in GPS receivers. A microprocessor-based design is highly reconfigurable and easy to develop and debug but not low power enough for mobile applications. The software overhead in tracking loops implemented on a microprocessor can be avoided with hardware implementation of the tracking loops on an Application-Specific Integration Circuit (ASIC). The low power asynchronous GPS baseband processor architecture in [1] achieves low power by allowing each subsystem to operate at its natural frequency without clocking and by employing arbitrated hardware tracking loops. On power-up, a host system initializes the receiver with system configurations, tracking loops parameters, and Doppler frequencies and acquisition power thresholds of six available satellites. An asymmetric acquisition scheme allows each channel to perform just code phase acquisition after initialization and to then track continuously. In this paper, we will describe and analyze the performance and robustness of the asymmetric acquisition algorithm introduced in [1] in greater detail. With such an acquisition scheme, the receiver does not need a dedicated bank of correlators for full acquisition but can re-use the same correlators used for tracking, resulting in minimal hardware footprint on a GPS ASIC. We will also describe the architecture of the asynchronous ASIC implementation of the Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) and present an analysis of the power, size and accuracy trade-offs for the tracking loops.
Published in:	Proceedings of the 25th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2012) September 17 - 21, 2012 Nashville Convention Center, Nashville, Tennessee Nashville, TN
Pages:	408 - 414
Cite this article:	Tang, Benjamin Z., Longfield, Stephen, Jr.,, Bhave, Sunil A., Manohar, Rajit, "Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy," Proceedings of the 25th International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2012), Nashville, TN, September 2012, pp. 408-414.
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