BINARY PROCESSING AND DISPLAY CONCEPTS FOR LOW-COST OMEGA RECEIVERS

R. W. Lilley

Peer Reviewed

Abstract:	A 6-bit sensor processing method based on a digital, memory-aided phase-locked loop (MAPLL) and BCD rate multiplier clock synchronising, provides building blocks for low-cost Omega receivers. The method has been implemented in flight-test hardware to provide raw Omega phase data suitable for direct interface with a microcomputer navigation processor. Experimental results and simulation studies of airborne systems will be presented. This work has been supported by NASA Langley Research Center Grant NGR 36-009-017 for application to low-cost VLF methods for the general aviation pilot.
Published in:	NAVIGATION: Journal of the Institute of Navigation, Volume 22, Number 3
Pages:	244 - 251
Cite this article:	Lilley, R. W., "BINARY PROCESSING AND DISPLAY CONCEPTS FOR LOW-COST OMEGA RECEIVERS", NAVIGATION: Journal of The Institute of Navigation, Vol. 22, No. 3, Fall 1975, pp. 244-251.
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