Description: The technology described here is described fully in an ION paper (All-Digital GPS Receiver Mechanization by Peter Ould and Robert Van Wechel) which we presented at the ION Aerospace Meeting in Trevose, PA in April 1981. The paper was then published in the Fall 1981 issue of the Journal of the Institute of Navigation, and in Volume II of the ION Red Books on GPS. The project was initiated in 1977 and was a company funded program. Despite the fact that this single channel C/A code GPS receiver version never saw production, it is viewed by many as the first digital (pre-correlation) GPS receiver and laid the groundwork for digital multi-channel GPS receivers. The discussion below provides further historical information, and information on the goals of the development.
The technical goals of our digital GPS receiver development were:
To use digital correlation to overcome the analog receiver limitation of only being able to implement a few analog correlators. With digital matched filters, much faster acquisition was feasible, and we needed fast acquisition for the applications we had in mind, such as missile tracking and submarine applications.
It was obvious that with digital signal processing implemented in highly integrated digital circuits that it would eventually be feasible to build GPS receivers with many channels, one for each satellite signal, that would be very small, low power and cost-effective.
Existing technology for code range measurement had shortcomings. The common practice of the time was to slew a PRN code generator to get it code-locked to the received signal, and then use counters to count clocks and epochs of the code generator to measure range. This resulted in much complexity, and required very high frequency clocks to get good accuracy. Our concept was to build the code generator so it could be initialized at any desired chip in the PRN sequence. In the case of P-code, we could initialize the P-code generator at any chip of the week-long sequence given a time-of-week word. When this capability was implemented in the code-tracking feedback loop, it was immediately known when code lock was obtained for the chip that corresponded to the time-of-week.
The same consideration existed in Numerically Controlled Oscillator (NCO) technology. Previous technology used hybrid analog-digital methods. With an NCO, the exact fractional time within the code chip can be set, making it unnecessary to measure this delay after-the-fact. As a result of this, we were able to build a code tracking loop in which the integer number of code chips (time-of-week for P code) was precisely known from the setting of the code generator, and the fractional chip value was known precisely through setting the code NCO. This provided range measurement as an inherent part of the code loop feedback process.
Another goal we had in the initial development of the receiver was to have a tracking mode where the tracking loops were all integrated together in a Kalman filter. This was to be a mode in which the benefit of tracking all the signal in the Kalman filter would lower the overall tracking threshold, thus making a more sensitive receiver. This goal has recently been met in our receivers and in that of many others and is referred to as Deep Integration or Deep Coupling. This goal was not achieved in this early development project for the dual reason of it being beyond the state of the computer art of the day, and also it was a task beyond the resources available to the project. The architecture went forward with conventional separated code and carrier tracking loops, one for each satellite signal.
Our initial receiver design as described in the original ION paper did not close the carrier loop digitally. The carrier NCO output was converted to analog and fed back to the last I-Q conversion in the RF down-converter. This was sort of an oversight, but since we were only building single channel receivers initially, it wasn't of much concern. Later, in 1984, when we extended the architecture to build multiple channel receivers, we implemented the carrier NCO feedback using a complex multiply in a read only memory (ROM). This allowed many channels to be implemented digitally without the addition of more analog circuitry and additional analog-to-digital (A/D) converters.
The initial breadboard receiver as shown in the pictures consisted of an RF down-converter unit (Figure 1), and a digital signal processor (Figure 2) which was used as a peripheral to a PDP-11/70 minicomputer. The RF down-converter shown was a compromise or fallback design and was much larger than originally planned. The original plan was to be on three 6" by 6" circuit boards. However, there were so many problems with this unit that it was abandoned and the larger unit shown in the picture was assembled and used with both the first and second generation digital signal processors.
The first generation digital signal processor (Figure 2) operated on C/A code only, and had two types of correlators. One was a 64 tap digital matched filter used for acquisition only and the second was an early-prompt-late correlator built with discrete digital logic. This system was used with the PDP-11/70 computer which was programmed in both assembly language and Fortran.
This signal processor was followed by a second generation signal processor which was developed using Motorola 68000 microprocessors. Both the first and second signal processors are described in the ION paper. The RF down-converter shown in Figure 1 was used with both signal processors. The second generation signal processor handled both C/A and P code. The P code generator is shown in Figure 3. The architecture of this processor is described in the ION paper. The signal processor was housed in a Motorola Exormacs (Figure 4), which was the development station for the 68000 microprocessor.