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Session A5: Receivers for New Space-Based Sources

Low-Power, Lightweight Satellite Navigation ASIC and Receiver Development
Scott Minas, AFRL; Nareshbabu Jarmale, Mayflower Communications Company Inc.
Location: Ballroom C
Date/Time: Tuesday, Jun. 4, 9:15 a.m.

Air Force Research Laboratory (AFRL) has developed a concept called Lightweight SatNav (LWS) that supports military users with stringent Size, Weight, and Power-Cost (SWaP-C) requirements. This new signal will be broadcast in testing from Navigation Satellite Technology-3 and Space Development Agency Tranche 1 and 2 satellites. The primary goal of LWS is to develop a system that is more robust than commercial receivers using open signals from GPS and other GNSS, while supporting significantly lower SWaP-C than modernized military User Equipment (UE) which utilizes M-Code. Proposed applications for this concept include hand-held and wearable military devices, micro-unmanned aerial vehicles (UAVs), unattended sensors, smartphones and other devices that make up the ever-growing, “Internet of (military) Things.” Other objectives include reducing the key distribution burden on the end user and accelerating the fielding of UE by implementing an alternative security architecture; and finally, to explore the “art of the possible” with regards to receiver power consumption.
Addressing this last objective, Mayflower, is developing a low-power LWS receiver design with an objective goal of less than 100mW continuous tracking power. The low-power objective of this receiver will be achieved by developing a custom Application Specific Integrated Circuit (ASIC) System-on-Chip. Integral to this work has been trade studies to analyze the impact (on power draw, acquisition, and tracking performance) of cryptographic key size, simultaneous tracking channels, supported frequencies, signal design, and interference mitigation filtering. These trade studies will affect the final digital ASIC design.
A prototype LWS receiver has been developed by Mayflower (Mayflower Prototype Lightweight receiver-MPLR) on an FPGA-based software-defined platform. This FPGA platform will implement and test the LWS receiver features and it will be used as a baseline design to guide the ASIC design and its power consumption.
This presentation at JNC 2024 will include trade-off analysis results via detailed high-fidelity modeling and simulation of LWS receiver design while addressing the low power objective. The presentation will also include results of testing of the MPLR receiver for LWS signal acquisition and tracking performance using signals from a LWS signal generator both in a laboratory environment as well as recorded LWS data from NavFest 2024.

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