Logan Reich, Sanjeev Gunawardena, Air Force Institute of Technology; Michael Braasch, Ohio University

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Satnav SDRs present many benefits in terms of flexibility and configurability. However, due to the high bandwidth signals involved in satnav SDR processing, the software must be highly optimized for the host platform in order to achieve acceptable runtimes. Modules such as sample decoding, carrier replica generation, carrier wipeoff, and correlation are computationally intensive components that benefit from accelerations. An architecture has been developed which allows for the components that must be high performance to be swapped out with versions that make use of accelerators such as FPGAs, GPUs, and vectorized instructions in the CPU (Gunawardena, 2021). Other modules are left in higher level language for ease of use. This differs from some previous projects which do not provide the same level of configurability and granularity that allows for modules to be swapped out without changing code. For the purposes of this paper, we will target general CPUs using Single Instruction Multiple Data (SIMD), multithreading, and bitwise methods. Both SIMD and multithreading accelerations have been previously discussed as applied to sample decoding (Reich et al., 2022). The target system for this paper is x86 64, extended with the Streaming SIMD Extensions (SSE) and Advanced Vector eXtensions (AVX) instruction sets. These 128-bit and 256-bit operations are used in conjunction with bitwise methodologies to perform many operations per instruction in parallel. In addition, these tasks are divided among several threads running concurrently. None of these parallelization techniques are invoked by default and must be specifically written into the program. This paper discusses the process of including these accelerations as well as extensive benchmarking results as compared to a naive C++ implementation. The results of this paper are intended to provide guidance on future optimizations to satnav SDR receivers.