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Session P5a: Present and Future Clocks for Space

Development of a Clock Ensemble Testbed
H. Kettering, N. Ristoff, E. Bergerson, and J. Camparo, The Aerospace Corporation
Location: Beacon B
Date/Time: Thursday, Jan. 25, 2:58 p.m.

Clock ensembling is not solely associated with building national timescales (e.g., UTC(NIST) and UTC(USNO)), but also for generating a system clock (e.g., a satellite clock) with better timekeeping performance and reliability than any single member of the onboard clock ensemble. As an example, one could imagine combining signals from several onboard chip-scale atomic clocks (CSACs) and oven-controlled crystal oscillator (OCXOs) to create a better onboard “paper” clock than any individual CSAC or OCXO on the satellite bus. Additionally, as we look to develop timescales for lunar and Martian PNT there will be a need for extraterrestrial timescales to remain synchronized and syntonized to UTC(BIPM) without continuous contact to a terrestrial signal. Clock ensembling will be the best way to create a robust lunar and Martian timescale, with the local (e.g., lunar) timescale employing a host of low to moderate size, weight and power (SWaP) clocks with very diverse timekeeping capabilities (e.g., CSACs, OCXOs, and GPS-like atomic clocks).
Unfortunately, while the timekeeping community has great experience ensembling clocks of similar quality to create a timescale, we have little to no experience with ensembling clocks of widely diverse timekeeping ability. Further, we have little experience with developing clock ensembling algorithms that are highly robust to ensemble-member failures. To address these questions, we have embarked on a long-term project to develop and utilize a hardware/software clock-ensembling testbed, with the goal of developing and testing ensembling algorithms that can work with a wide variety of clock types (i.e., clocks with widely different Allan deviations) and that are robust to ensemble-member failures.
In this presentation we will provide an overview of our clock ensembling testbed, and our ability to simulate in hardware the degradation of an ensemble member’s white frequency noise and random-walk frequency noise. As an illustration of the clock ensembling testbed’s utility, we will provide initial results showing the response of NIST’s AT2 algorithm (employing a five-clock ensemble) to an ensemble member’s increasing white frequency noise and random-walk frequency noise.

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