Title: FPGA-Optimized GNSS Receiver Implementation Techniques
Author(s): H. Stewart Cobb
Published in: Proceedings of the 21st International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2008)
September 16 - 19, 2008
Savannah International Convention Center
Savannah, GA
Pages: 2326 - 2331
Cite this article: Cobb, H. Stewart, "FPGA-Optimized GNSS Receiver Implementation Techniques," Proceedings of the 21st International Technical Meeting of the Satellite Division of The Institute of Navigation (ION GNSS 2008), Savannah, GA, September 2008, pp. 2326-2331.
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Abstract: This paper presents techniques for implementing GNSS receiver channels which work well within FPGAs (Field Programmable Gate Arrays). FPGAs are now available which are large enough to implement the custom signal-processing functions for an entire GNSS receiver. While cost-prohibitive for mass production, FPGA implementations are entirely suitable for research or even for small-volume production. They provide the ability to alter the signal processing logic quickly and at low cost, as the needs of the product or the research program change. To make best use of an FPGA, however, requires an approach to signal processing design which differs from the traditional ASIC (Application Specific Integrated Circuit) approach. This paper presents techniques for minimizing logic and interconnect in the design of GNSS receiver channels, making them more suitable for FPGA implementations. These techniques include the use of serial arithmetic, time-sharing, and the CORDIC algorithm. Other techniques are presented which take advantages of special features of FPGAs from certain manufacturers, such as shift registers, large dual-port memories, and high-speed serial transceivers. These techniques have been used to implement the equivalent of a GP2021 chip (a well known 12-channel GPS C/A code correlator ASIC) on an FPGA which currently costs less than the GP2021 chip on the open market.